A demand for high-density memories has increased with an advance in a semiconductor fabrication technology. U.S. Pat. No. 6,545,900 discusses a technique for realizing high-density packing of memory cell blocks. As illustrated in FIG. 1A, cross-shaped memory cell blocks 10 including a memory cell array A and peripheral circuits P surrounding the memory cell array A are arranged in an offset manner. When the memory cell blocks 10 are arranged in a typical manner, as illustrated in FIG. 1B, empty spaces 14 are formed between the memory cell blocks 10. Therefore, chip area may be wasted. Furthermore, as the area of the peripheral circuits P increases, the amounted of wasted chip area increases as illustrated in FIG. 1C. To address this issue, U.S. Pat. No. 6,545,900 suggests arranging the memory cell blocks 10 in the offset manner to restrain the occurrence of the empty spaces 14.
The technique discussed in U.S. Pat. No. 6,545,900 may realize the high-density packing, only when a ratio of a length L1 of the horizontal side in each memory cell array A to a length M1 of the horizontal side in each peripheral circuit P is 2 to 1 or only when a ratio of a length L of the vertical side in each memory cell array A to a length of the vertical side in each peripheral circuit P is 2 to 1. For example, as illustrated in FIG. 1D, the empty spaces 14 occur between the memory cell blocks 10 in a case of L1:M1≠2:1 or L2:M2≠2:1. For this reason, in this technique there may be a restriction on the length of the memory cell block for the purpose of realizing the density arrangement of the memory cell blocks 10.
As further discussed in Japanese Patent Publication NO. 2007-200963 and illustrated in FIG. 1E, memory cell blocks 20 are designed in an “L” shape and the memory cell blocks 20 are arranged in a point-symmetric manner. However, in this technique the memory cell blocks 20 are closely arranged to realize the high-density packing only when a length L1 of the longer side in each memory cell block 20 is about the double of a length L2 of the shorter side thereof. For example, as illustrated in FIG. 1F, an empty space 24 occurs between the memory cell blocks 20 in a case of N1:N2≠2:1. Therefore, Japanese Patent Publication NO. 2007-200963 also has the restriction on the length of each memory cell block 20 for the purpose of realizing the dense arrangement with no empty space 24, like U.S. Pat. No. 6,545,900.